1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device, which can reduce the resistance between a silicon substrate and a contact plug and thus increase the operation speed of the device.
2. Description of the Prior Art
As the high integration level of a semiconductor device is increased, the linewidth required to realize the device is gradually reduced. According to this tendency, various processes are studied and developed to make device characteristics good. Particularly, in order to improve the operation efficiency of a device, there are made new attempts to develop a contact-forming process, which can reduce the resistance between a contact plug and a silicon substrate.
In semiconductor devices according to the prior art, a contact plug based on impurity-doped polycrystalline silicon was formed on a silicon substrate. If the interface between the silicon substrate and the polycrystalline silicon contact plug is ideal, there will be no resistance caused by a difference in work function, because the contact between the silicon substrate and the contact plug is the contact between the same materials. Namely, if the silicon substrate and the polycrystalline silicon contact plug have the same impurity concentration, the resistance therebetween will be very low.
However, the resistance between the polycrystalline silicon contact region and the silicon substrate is generally relatively high. Generally, a N-doped contact region having a contact area of 0.1 μm2 has a high resistance of about 10 kΩ.
Such a high resistance is known as attributing to native oxides and carbon-containing residues formed at the interface between the polycrystalline silicon contact plug and the silicon substrate.
Generally, in a process of forming a polycrystalline silicon contact plug according to the prior art, although the deposition of polycrystalline silicon is carried out immediately after conducting a wet cleaning process, an increase in this contact resistance cannot be effectively inhibited.
In the prior wet cleaning process, the silicon substrate is cleaned with non-organic volatile compound solution and de-ionized water. Thus, the prior wet cleaning process does not effectively prevent the native oxides and the carbon-containing residues from being formed on the surface of the silicon substrate. As an alternative method to overcome an increase in resistance according to a reduction in contact area as described above, there is a method in which the selective epitaxial growth (SEG) of silicon is used to prevent the resistance increase caused by the native oxides and the grain boundary. In this silicon SEG, low-pressure chemical vapor deposition (LPCVD) is mainly used. Moreover, as reaction gas, dichlorosilane(DSC)/H2/HCl or monosilane(MS)/H2/HCl is mainly used. In addition, the silicon SEG generally needs to be conducted at a high temperature higher than 800° C.
This high-temperature process is a factor making semiconductor device characteristics difficult to be ensured. Accordingly, there is urgently required to develop a process, which allows the effective growth of monocrystalline silicon having low contact resistance at the lowest possible temperature.
Particularly, in the prior art, there is required a process of thermally treating the silicon substrate with hydrogen (H2) gas at a high temperature higher than generally 800° C., before conducting the silicon SEG.